The present invention relates to processing data in data communication systems and data storage systems, and in particular to encoding and decoding of data for purposes of error correction.
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Error correction is an important aspect of providing reliable data delivery in data communication systems and reliable data storage and access in data storage systems. An error correction technique that is commonly employed is called Low Density Parity Check (LDPC). LDPC is a linear block coding technique that can provide performance close to the theoretical maximum of the communication channel, using an iterated soft-decision decoding approach.
The increasing use of mobile devices presents challenges in error detection and error correction. For example, the compact dimensions of mobile devices typically impose a small footprint requirement for its electronic circuits. Mobile devices are becoming increasingly more like personal computers, requiring large storage capacity and high speed operation in a highly mobile configuration. Accordingly, high capacity, high speed flash memory is a common design element in mobile devices, and LDPC would be a suitable error correction technique.
However, high speed decoders that employ LDPC are typically characterized by high complexity (i.e., high gate count for implementing the logic, and consequently large silicon area) and high power consumption requirements, which conflict with the constraints of mobile devices. In addition, a flash memory device typically employs “hard decision” block codes, which means that for every input and output a hard decision is made whether it corresponds to a one or a zero bit. Soft data (e.g., reliability information) that is required with “soft decision” techniques such as LDPC may not be available in a particular flash memory design.